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I am an engineer at AMD. I have a strong background in computer architecture, fabric interconnect, storage virtualization and x86 virtualization. I came to AMD as part of the SeaMicro acquisition. At SeaMicro, I invented and implemented the fabric software routing subsystem, as well as architected and led the implementation of a virtualized storage subsystem. Before SeaMicro, I helped build VMM record-replay technology at VMware, which is the core technology in VMware's VM Fault Tolerance (FT) infrastructure software.

The best way to reach me is via email. My email is   m i n . x u 2 -at- mycompany dot com.

News: AMD acquired SeaMicro!


Ph.D. Electrical Engineering     May 2006
University of Wisconsin-Madison

Dissertation: Race Recording for Multithreaded Deterministic Replay Using Multiprocessor Hardware
Advisor Mark Hill and Rastislav Bodik.
Thesis: pdf
Defense Presentation: six-per-page pdf, two-per-page pdf, or ppt


Please respect the copyrights.

Permission to copy without fee all or part of this material is granted\nprovided that the copies are not made or distributed for direct commercial advantage. To copy otherwise, or to republish, requires a fee and/or specific permission of the authors and/or ACM/IEEE.

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  1. A Regulated Transitive Reduction (RTR) for Longer Memory Race Recording.,
    Min Xu, Rastislav Bodik and Mark D. Hill,
    Submitted to 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Oct. 2006.
  2. A Serializability Violation Detector for Shared-Memory Server Programs,
    Min Xu, Rastislav Bodik and Mark D. Hill,
    ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation (PLDI), June 2005.
  3. A "Flight Data Recorder" for Enabling Full-system Multiprocessor Deterministic Replay,
    Min Xu, Rastislav Bodik and Mark D. Hill,
    30th International Symposium on Computer Architecture (ISCA), June 2003.
  4. An Efficient Model for Frequency Dependent On-Chip Inductance,
    Min Xu and Lei He,
    Great Lakes Symposium on VLSI-2001.
      Paper: pdf
      Presentation: pdf

Workshop and Tutorial:

  1. ReTrace: Collecting Execution Trace with Virtual Machine Deterministic Replay,
    Min Xu, Vyacheslav Malyugin, Jeffrey Sheldon, Ganesh Venkitachalam and Boris Weissman,
    Third Annual Workshop on Modeling, Benchmarking and Simulation, held in conjunction with the 34th Annual International Symposium on Computer Architecture, June 2007.
  2. [Tutorial] GEMS: Multifacet's General Execution-driven Multiprocessor Simulator,
    Michael R. Marty, Bradford Beckmann, Luke Yen, Alaa R. Alameldeen, Min Xu, and Kevin Moore,
    International Symposium on Computer Architecture (ISCA), June 2006.
      Presentation: ppt
  3. Evaluating Non-deterministic Multi-threaded Commercial Workloads,
    Alaa R. Alameldeen, Carl J. Mauer, Min Xu, Pacia J. Harper, Milo M.K. Martin, Daniel J. Sorin, Mark D. Hill and David A. Wood,
    Computer Architecture Evaluation using Commercial Workloads (CAECW-02), February 2002.
      Paper: pdf
      Presentation: pdf


  1. A Hardware Memory Race Recorder for Deterministic Replay,
    Min Xu, Rastislav Bodik, and Mark D. Hill,
    IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences, January-February 2007.
  2. Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset,
    Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood,
    Computer Architecture News (CAN), Volume 33, Issue 4, 92-99, November 2005.
  3. Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization,
    Kevin M. Lepak, Min Xu, Jun Chen and Lei He,
    ACM Transactions on Design Automation of Electronic Systems, Volume 9, Issue 3, Pages 290 - 309, 2004.
  4. Simulating a $2M Commercial Server on a $2K PC,
    Alaa R. Alameldeen, Milo M.K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin, Mark D. Hill and David A. Wood,
    IEEE Computer, February 2003.
      Paper: pdf
      Presentation: ppt

Technical Reports:

  1. Modeling and Layout Optimization for On-chip Inductive Coupling,
    Lei He and Min Xu,
    ECE Report 2000-01.
    Paper: pdf

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